In general, a complementary metal oxide semiconductor (CMOS) image sensor (CIS) includes a photodiode and a transistor circuit for each unit pixel. Typically, a number of metal layers and vias are formed above the photodiode and transistor circuit to provide signal and power lines to devices such as the transistor circuit.
According to related arts, metal and via formation processes are performed without considering the light path. Therefore, a misalignment or overlay variation may occur during formation of a microlens. The misalignment or overlay variation can scatter or reflect the incident light. This causes light loss and, thus, the image quality of a product is deteriorated.
Typically, in a photolithography process for the microlens, the microlens is aligned using a top metal layer. This can further aggravate the light scattering/reflection limitation when overlay variation in the metal and via processes occurs.